The trend in integrated circuit (IC) design is to produce circuits that can be operated at reduced power supply voltages (Vcc). Power reduction constraints have reduced the industry standard power supply voltage from 5 volts to 3 volts. However, not every IC only operates at 3 volts. A transition time thus exists where certain chips, such as timing chips, must work with both 3 and 5 volt power supply voltages.
It is desirable to have a low-noise customized clock chip that can work with both 3 volt and 5 volt power supply voltages. A clock duty cycle is measured at 1.4 volts (for a TTL input). A desired duty cycle performance may be, for example, about 50% across process, temperature and voltage ranges for output frequencies up to 140 MHz (5V) or 122 MHz (3V). A desired slew rate may be, for example, between 1 V/ns-2 V/ns. Clock jitter should be relatively low. For example, less than 250 ps jitter is acceptable. Traditional clock drivers may not meet these specifications which may be required for certain modern IC applications.
Some approaches which achieve a 50% duty cycle (measured at 1.4V) at 5 volts implement a pad driver that has a large N-channel pull down transistor. This creates a faster falling time on each clock edge and effectively adjusts the output driver's threshold from 0.5 Vdd to 0.3 Vdd. As a result, a desired duty cycle is achieved when measured at 1.4V which may use a 4.5-5.5 volt power supply voltage. FIG. 1 illustrates a comparison between a pad operating at 5 volts and an otherwise identical pad operating at 3 volts. When the pad above is operating at 3 volts, the rising edge becomes much slower and the measuring point is closer to Vcc. As a result, a very low duty cycle is realized. The precise change in duty cycle depends on the output edge rates. At 5 volts, an excessive amount of noise is produced because the pull-down process is much faster. Tests have shown that the duty cycle produced when the pad is operating at 3 volts may be unacceptable for certain modern IC applications.
Several approaches may realize a 50% duty cycle at both 3 volt and 5 volt operating voltages. One approach uses a programmable element to control a portion of a pull down transistor. This allows the adjustment of the effective output threshold for the desired operating voltage. A major disadvantage of this approach is that the operating voltage must be known while building the programming vectors necessary for the manufacturing of the IC. After the internal fuses of the IC are programmed, the IC typically works only at the specified operating voltage. This tends to increase the complexity of manufacturing as well as the time necessary to generate samples. For example, a manufacturer generally must stock both 3 volt and 5 volt versions of the same part to meet demand.
A second approach may realize a 50% duty cycle at both 3 and 5 volt operating voltages by using an on-chip voltage detector in place of the programmable element. The effect on signal control in the output pull down transistor is the same as in the approach discussed above. However, the second approach provides the advantage of being able to work with either voltage range (e.g., 3.0-3.6V or 4.5-5.5V). One disadvantage of the second approach is that the part tends to operate erratically in the voltage range between 3.6 and 4.5V. This erratic behavior is often directly translated into output jitter. Additionally, it is often difficult to reliably detect a voltage between 3.6 and 4.5 volts under noisy operating conditions.
A third approach may realize a 50% duty cycle at both 3 and 5 volt operating voltages by increasing the edge rates of the output signal. This improves the duty cycle by reducing the time difference between the output threshold voltages. The third approach may be undesirable because a faster edge rate increases the on-chip noise problems and the EMI radiation. The required edge rates for the desired duty cycle performance are three to five times faster than current produce able values. Increased on-chip noise resulting from increasing the edge rates directly increases the part jitter.
A fourth approach realizes a 50% duty cycle at both 3 volt and 5 volt operating voltages by changing the specifications to work around the duty cycle problem. For example, the duty cycle specification may only be met at a lower frequency. This may also be undesirable since conditions under which parts meet duty cycle and other specifications are becoming stricter with time.